EP O 1 79 291  B1        .     .
For example, let _it be assumed that the 3 x 3 window 71 samples the bit_ panern_ shown i_ 'F_i__g. 4A. The
bit pattern ''IOO'' of the first scan line, ''1 IO'' of the second scan line and ''IOO'' of the thifd SCan line afe
concatenated, or serially conencted to ''IO01 I01 OO'', and this concatenated bit panern iS stOred in the
pattern register 72, and then suppl_ied to the conversion table means 73, Refe Fring to Table 3, at exemplary
_  entry No. 1, the conversion table 73 has the above address and generates the output panern ''IO0IO0IOO''.
The output panern ''IO0IO0IOO'' is supplied to the 3 line bu_er J6 through an outPut line J4 and a gate 75,
The gate 75 operates to assemble the serial output bit panern ''IO01 O01 OO'' to the three l__ne panern shown
__n Fìg. 4B. Thus, the input bit panern of Fig. 4A has been converted to the bit pa_ern of Fig. 4B.
The remaining entries 2 through 7 of Table 3 show the addresses and output bit panerns for Figs. 4C
Io  through 6D and Figs. 3A and 3B.                       _
It._s noted that in the cases of Figs. 4C, 5A, 5C, 6A and 6C, the bit panern enclosed by _o windows 71 is
used as a s__ngle address, and in the case of F._g, 3A, the bit panern enclosed by four windows J1 is used as a
single address. The reasons for the use of plural windows for forming a single address, will now be
described. First referring to Fig. 4A, its b__t panern has all ''O'' bits in the third column, in other words, the
1_  boundaries from black to white for all scan l__nes are found in this single window. In contrad._stinction, the
f__rst 3 x 3 window of Fig. 4C does not include the black to white boundaries for all scan línes with__n it, so __t
can not be determined whether the black pels or elements continue into the subsequent window, or not.
Accordingly, the second window is joined to the f__rst window. The second window conta__ns all ''O'' bits in
the th._rd column, wherebv the black to white boundaries for all lines exist within the first and second
2o  w._ndows.
To control the joinder of the subsequent w_indow to the prec_ eding windowlsl, the convers__on table 73
generates the Control signal ''Panern Save'' on the control line 77 when a panern, which does not include
black to white boundar__es for all lines, is appl._ed to the table 73, The Panern Save signal has a unique
panern, e.g. ''1 1 1 1 1 1 1 1 1'', which can be distinguished from all other output b__t panerns, as shown __n the
z_  entr__es n-6 through n in Table 3. For the case of F._g. 4C, the generat__on ofthe Panern Save output __s shown
in entry n-6 of Table 3.
As a further example, in the process ofthe bit panern of Fig. 3A. the supply ofthe b,_t panern of the first
3 x 3 window to the conversion table 73 produces the Panern Save output ''1 1 1 1 1 1 1 1 1 '' causes a signal on
the control l__ne 77, as indicated._n the entrv n-2. and no output panern is supplied to the output line J4. The
3o  Panern Save s__gnal applied to the panern register 72 causes the bit panern of the second w._ndow to be
subsequently stored, concatenated to the b._t panern ofthe first window, in the panern reg__ster72. Now, the
combined bit panern of the first and second w__ndow is applied to the conversion table 73 as a s_ingle
address, as ind__cated _in the entry n-1, and a _Panern Save signal is produced on the line 77 a_gain. In
response to the Panefn Save signal, the panern regi Ster 72 storeS the b._t panern of the third window along
3_  with the first and second bit panerns. The combined bit panern __s supplied to the conversion table 73,
wh._ch generates the Panern Save signal on the line 77, as shown in the entrv n of Table 3, Then, the panern
register 72 stores the bit panern ofthe fourth window also, and the combined bit panern ofthe fìrstthrough
founh wìndows._s applied to the conversion table 73, as indicated in the entrv 7 of Table 3, wh_ich produces
the bit patern correspond__ng to that of Fig. 3B on the output line 74. Thus, the output bit panern stored in
_o  the 3-line bu_er 16 through the gate 15 represents the bit panern of Fig. 3B.
The b__t panern __n the 3-line buffer 76, which has been pre-processed in accordance with the present
invent_ion,._s supplied to the convent._onal compression dev,_ce 78, in Fíg. 7, which compresses the b__t
_ panern from the 3-l__ne buffer 76._n accordance with the _o-dimensional coding scheme of the CCITT
Recommendatìon T.4, for example.
_       _ _ ___ _ - _ -__ _  _ _ _ -_  _ __ _  __  - _ __ _ _     _           -  - _   _
Description of a Second Embodiment             -   _  _ -  _ _
The Figs. 8 through IO show a second embodiment of the present ìnvention. In this embodiment, the 2
pel x 4 pel w__ndow 81 shown in Fig. 8 samples or picks up each arrav of 2 x 4 image bits in the document
image 82. The stan position of the 2 x 4 pel window is at the upper left corner of the document image 82,
_o  __.e. PeIS LIC1-LIC4 and L2C1-L2C4. The 2 X 4 pel w._ndOW 81 pfOgeSSiVely mOVeS Or ShiftS towardS the
_      f.ight-most pel position C,.
When the 2 x 4 window 81 after having staned from the upper left-most pel pos._tions,._.e., the said
LIC1-LIC4 and L2C1-LzCQ, reaCheS the F._ght edge Ofthe SCan IineS L1 and L21 the 2 X 4 W__ndoW 81 retUrnS to
the ne Xt Stan pOSitiOn L2C1-L2C4 and L3C1-L3C41 and SCanS thiS ne Xt COUple Of SCan lineS L2 and L3. AS the 2
__  X 4 pel WindoWs 81 SCans the.document image 82, the pel converSion Shown in Fìg, 9 is performed. One
_,           example of the conversìon is shown in Figs. 8 and IO. F,_gure IO(A) shows a first step in which the b*_-Ievel
image data Of SCan lineS L1 and L2 afe fetChed intO an inpUt bUffer, n Ot ShOWn. Then, the 2 X 4 pel WindOW __S
SeqUentially mOVed ffOm the firSt pel C1 tO the _aSt pel C,. DUF__ng eaCh Shift Of the SeqUential mOVementp 8
pels within the 2 x 4 pel window 81 are inspected as to whether the 8 pels match with one of the panerns 1
6o  throUgh 4 Of F__g. 9, lf Yes., the 8 pels are replaced by one ofthe panerns 1 1 through 14. If No, the ConVerSion
.  Or replaCement iS n Ot made, that iS, the Ofiginal peIS afe n Ot Changed. The fetCh Of the 2 X 4 peIS and the
comparison of the 2 X 4 pels w__th the panerns 14 in Fig. 9 could be performed by a sim.ilar circuit
arrangement aS the panern register 72 and the con_ vers__on table means 73 in Fig. J..
A matCh tO the pane Fn 1 iS fOund for the peIS LIC3-LIC6 and L2C3-L2C61 and theS_ eight peIS afe
__  replaCed by the panern 1 1. ThiS feplaCed panefn 1 1 iS ShOWn by the SOl__d Iine I01 in FIG. IO(B). The ne Xt
_     6           ,                  .     _